Webinar – Toward Low Power Cryogenic Si MOSFETs

High-performance computing based on the von Neumann architecture is facing increasing power and energy-efficiency challenges. Cryogenic computing, spanning von Neumann, neuromorphic, and quantum systems, has emerged as a promising approach to enable highly energy-efficient data processing. CMOS technology remains a key platform for implementing these systems, but conventional devices optimized for room-temperature operation face fundamental challenges at cryogenic temperatures. As the temperature approaches absolute zero, the subthreshold swing (SS) becomes increasingly limited by band-tail effects, while the threshold voltage increases due to bandgap widening and Fermi-level shifts. These effects degrade transistor performance and pose significant challenges for low-power circuit operation and design.

This presentation discusses the key physical and technological challenges of cryogenic CMOS and explores device and material strategies for overcoming these limitations. In addition, the feasibility of cryogenic memory based on a single fully depleted silicon-on-insulator (FDSOI) MOSFET will be presented. By integrating memory and logic functionalities within a CMOS-compatible platform, this work points toward highly energy-efficient and scalable computing systems operating at cryogenic temperatures.